SYSTEM HACKED // MATRIX MODE ACTIVATED
user@anubhab-portfolio:~/trivia

HPC Control Center

Clock Freq 1.0 GHz
Graph Density Medium
Active Cores Auto
System Status:

Hi, my name is

Anubhab.

I

I'm a researcher bridging the gap between Deep Learning Algorithms and Specialized Hardware.

I focus on Hardware-Software Co-design and Deep Learning Compilers to unlock peak performance on Sparse Accelerators.

I am actively seeking PhD opportunities in Deep Learning Compilers & Hardware-Software Co-design.

01.

About Me

My research focuses on Deep Learning Compilers, High Performance Computing, and Hardware-Software Co-design for neural networks on heterogeneous hardware. I specialize in compiler optimizations for resource-constrained environments like Edge AI and for specialized hardware such as Sparse Accelerators.

I leverage compiler infrastructures like MLIR to automatically generate efficient code. By designing modular compiler passes—from IR optimizations to backend-specific code generation.I aim to bridge the gap between high-level abstractions and silicon.

DL Compilers HPC HW-SW Co-design Sparse Accelerators Code Generation
Anubhab Avatar
02.

Where I've Worked

Research Assistant

BrainSeek Lab, IIT Madras

Aug 2025 - Present

Developing compiler pass pipelines in MLIR/LLVM to map sparse tensor operations to RISC-V vector extensions for Edge AI accelerators.

  • Designed the RICE Dialect: A custom MLIR dialect for optimizing Transformer workloads on RISC-V.
  • Built an instruction-scheduled ViT inference pipeline tailored for RISC-V architectures.
  • Improved LLVM/MLIR pass order by analyzing phase-ordering effects on code quality.
  • Yielded 1.5–2x speedups over scalar baselines for Transformer workloads.

Research Assistant

PACE Lab, IIT Madras

June 2023 - Aug 2025

Lead Designer of "Morphling": A multi-backend DSL synthesizer for GNNs that decouples algorithm specification from hardware scheduling.

  • Achieved speedups of 17x over PyG and 6.5x over DGL (geometric mean) on large-scale datasets.
  • Engineered a sparsity-aware execution engine reducing memory traffic on irregular workloads.
  • Implemented custom kernels (CUDA/OpenMP) and a distributed partitioner (MPI) with non-blocking training.

Collaborator

CNERG Lab, IIT KGP

April 2023 - June 2023

Contributed to an NLP project for detecting online hate speech using Transformer-based models.

  • Fine-tuned RoBERTa through rigorous hyperparameter optimization.
  • Implemented oversampling techniques to address class imbalance.

Data Engineer

Skuad Labs (Remote)

July 2022 - April 2023

Designed automated ETL pipelines for large-scale structured/unstructured datasets, improving data availability for analytics teams.

Software Intern

Raja Software Labs

Dec 2021 - May 2022

Optimized frontend performance for LinkedIn web components using Ember.js.

B.E. in Computer Science

Visvesvaraya Technological University

Aug 2018 - Jul 2022
03.

Projects

RICE Dialect for Torch-MLIR

MLIR RISC-V Compiler

A custom MLIR dialect for optimizing Transformer workloads on RISC-V. Implements high-level ops like Attention and SwiGLU with lowering passes to Linalg and vector intrinsics.

LLVM Custom Compiler Passes

C++ LLVM Static Analysis

Implemented core compiler analyses including Range Analysis (abstract interpretation), Andersen-style Pointer Analysis, Dependence Analysis for loop parallelization, and automatic array bounds checking.

MobileNet Compression Pipeline

Pruning Quantization PyTorch

End-to-end compression for MobileNet V2. Reduced model size by 7.3x (11.4MB to 1.56MB) via magnitude pruning and post-training quantization (W4A8) with <4% accuracy loss.

Static Analysis Visualizer

Visualization Clang Static Analyzer

Implemented the backend for LLVM/Clang Static Analyzer to parse and visually display detailed bug reports and code diagnostics.

04.

Talks & Publications

Publications

Morphling: Fast, Fused, and Flexible GNN Training at Scale

Anubhab, Rupesh Nasre. Submitted to IEEE TPDS, 2025 (Under Review).

2025

A One-Stop DSL for All Your GNN Workloads

Anubhab, Rupesh Nasre. IEEE HiPC Student Research Symposium.

2025

Morphling: A One-Stop DSL for All Your GNN Workloads

Anubhab, Rupesh Nasre. Invited Poster at IISc Computer Systems Workshop.

2025

Talks & Academic Service

Artifact Evaluator

CGO 2026, ACM/IFIP Middleware 2025

Invited Talk: "The Morphling Framework"

IIT Jammu (Upcoming, Dec 2025)

Invited Talk: "Optimized Code Generation"

IIIT Hyderabad (Upcoming, Dec 2025)

Speaker: EduHiPC 2024

Presented on behalf of Prof. Rupesh Nasre

Teaching Assistant

National Supercomputing Mission (NSM) Week, IIT Madras

Awards

Prime Minister's Special Scholarship Scheme; Google Code Jam Qualifier

05.

Skills & Interests

📚 Relevant Coursework

  • GPU Programming
  • Parallel Scientific Computing
  • Systems for Deep Learning
  • Program Analysis
  • Advanced Data Structures & Algorithms

Research Focus

Compilers

MLIR LLVM Clang Polyhedral TVM

Co-design & Hardware

HPC Sparse Accelerators Edge AI CUDA MPI OpenMP

Languages

C/C++ Python CUDA Verilog SQL
🎮

DOTA 2

Strategic Addiction

🍳

Cooking

Experimental Chef

ML Stack

  • PyTorch
  • TensorFlow
  • PyG
  • DGL
  • DistDGL

Top 5%

Techgig Code Gladiators

06. What's Next?

Seeking PhD Opportunities

I am actively looking for PhD positions in Deep Learning Compilers, Sparse Accelerators, and Hardware-Software Co-design. If you are recruiting prospective students or would like to discuss my research, please reach out.

Contact Me